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rev. 0.1 9/12 copyright ? 2012 by silicon laboratories AN725 AN725 a dvanced l ow p ower t echniques for sim3l1 xx d evices 1. introduction the system power budget of a low power system has two components: active and lo w power mode. active mode periods include an active core executing code or a larger number of active peripherals. in low power mode periods, the core enters a sleep state and fewer peripherals are active. figure 1. defining the power budget?active and low power modes sim3l1xx devices have several features to address reducing power consumption in all operational modes to achieve a longer product lifetime in battery-operated sys tems. this document addresses each of these features and provides guidelines for achieving low power consumpt ion in a variety of configurations and applications. 2. key points this key topics of this document are as follows: ?? how to reduce active mode time and power consumption ?? how to reduce low power mode power consumption ?? measuring the low power modes on an sim3l1xx mcu card ?? general power-saving tips 3. relevant documentation precision32? application notes ar e listed on the following websit e: www.silabs.com/32bit-appnotes. ?? an666: usage guide for e sim3u1xx,sim3c 1xx, and sim3l1xx dma and dtm modules ?? an720: precision32? optimization co nsiderations for code size and speed ?? an667: getting start ed with the silicon la bs precision32 ide ?? an670: getting started with the silicon labs precision32 appbuilder active mode low power mode
AN725 2 rev. 0.1 4. reducing active mode power consumption in active mode, the core is fetching instructions from memory and execut ing those instructions, and a large number of peripherals may be active at once. this section discusses ways to reduce t he sim3l1xx device power consumption in active mode (normal, pm1, pm4, or pm5). 4.1. dynamic ahb/apb clock scaling one of the easiest ways to reduce ov erall system power consumption is to reduce the active mode time, which maximizes the amount of time spent in the low power mode. if the longest path to the next low power mode is the execution of code (e.g., a math algorithm), then it is typically beneficial to run the ahb clock at the fastest spee d possible to reduce the time spent in active mode. if the longest path to the next low power mode is the transfer or collection of data through a peripheral, it is best to run the clock at the lowest speed required for the peri pheral. for example, if using the uart at 115200 baud and the core is waiting for data to finish transferring, then running the ahb and apb at the slowest clock to achieve 115200 baud may be the lowest power configuration. however, if data is being transferred memory to memory by the dma, running the clocks at the fastest speed possible yields the lowest power consumption. due to the clock system of the sim3l1xx devices, the ahb and apb clo cks can be dynamica lly changed quickly and easily using the clkctrl module based on the needs of the application. 4.2. using the dma and dtm modules the direct memory access (dma) and data transfer manager (dtm) modules help move data without core intervention. this reduces overall power consumption by removing the power consum ed during flash accesses. additionally, since the cortex-m3 is a load-store architecture where data is loaded into and out of registers only, multiple instructions are required to move data from one area of memory to another, so the dma and dtm may be faster than data moves by the core, depending on the ahb load. instead of performing the data moves, the core can eith er sleep using wait-for-inter rupt (wfi) or wait-for-event (wfe) instructions, or the core can perform other tasks in parallel, reducing the active mode time. for more information on how to use the dma and dtm modules, see ?an666:usage guide for e sim3u1xx,sim3c1xx, and sim3l1xx dma and dtm modules? on the silicon labs 32-bit application notes website: www.silabs.com/32bit-appnotes. 4.3. code optimization there are several different coding techniques, compiler, and library options available for the precision32 devices. these options will change both code size and ex ecution speed, which may result in power consumption savings in systems which aim to execute code in active mode as qu ickly as possible before ente ring a low power state. in addition to getting to the low power mode more quickly, changing the project settings may lead to smaller code footprints, compacting the c ode into a smaller area with fewer memory accesses. the power consumption benefits of code optimization for speed or size will vary depend ing on the project requirements and code. for more information on how to write efficient code and the various optimization settings, see?an720: precision32? optimization consideratio ns for code size and speed? on the silicon labs 32-bit application notes website: www.silabs.com/32bit-appnotes.
AN725 rev. 0.1 3 4.4. code dependency in addition to dynamic clo ck management, the power consumption of the sim3l1xx de vice will vary with the type of code the core executes. for example, if the core executes a complex math routine with branches, the pipeline will miss every time a branch is taken and new instructions mu st be fetched. this stall and fetch period causes more flash accesses, which increases power consumption. in addi tion, the core executes a wide variety of instructions and activates the memory bus to fetch data from ram or flash for use in th ese routines. in contrast, a string of nop instructions will take less pow er because the core isn?t ex ecuting complex instructions. the data shown in figure 2 does not use adaptive voltage scaling or any other techniques to change power consumption. all of these measurements were taken using the pll as the clock source with a higher spmd setting (i.e., reduced flash access frequency) at ahb freque ncies above 40 mhz. the apb cl ock is equal to the ahb clock, when the apb is enabled. as shown by the data, the flash access frequency (spmd) has a direct effect on the code that includes branches, since the core stalls when waiting fo r the new instructions, resulting in reduced power consumption. this means that it may be more efficient to run at a faster frequenc y with the same current consumption to reduce overall time spent in active mode. for the code that is a long st ring of nops, the core neve r has a pipeline miss and never stalls, so there is no change in power consumption with a different flash speed mode. for power sensitive applications, expe rimenting with various code styles and instruction mixes may result in reduced power consumption in active mode. figure 2. power consumption code dependency ahb and apb clock (mhz) current 20 25 30 40 50 45 35 nop code, no apb clocks enabled, all ldos at 1.8 v nop code, all apb clocks enabled, all ldos at 1.8 v complex code, no apb clocks enabled, all ldos at 1.8 v complex code, all apb clocks enabled, all ldos at 1.8 v spmd = 1 spmd = 2
AN725 4 rev. 0.1 4.5. adaptive voltage scaling sim3l1xx devices have scal able ldos powering the digital and memory modules on the device. these ldo outputs are factory calibrated to 1.8 v to handle all process and temperature variations, but this voltage is often much higher than the minimum voltage required by the digi tal and memory circuits. during normal operation, these ldo outputs can be set to a value less than 1.8 v to reduce the amount of excess power consumed by these circuits with some buffer to ensure correct operation. when the digital or memory ldos are sourced from the dc-dc converter, adaptive voltage scaling can also allow the ldos to track the dc-dc output voltage to utilize the higher efficiency of the dc-d c converter and reduce the losses in the regulators. figure 3. reducing power consumption with adaptive voltage scaling ahb clock (mhz) power (mw) 0 10 20 30 40 50 70 60 0 1020304050 digital ldo output fixed at 1.8 v digital ldo output scaled once at production test digital ldo output scaled adaptively by firmware
AN725 rev. 0.1 5 4.6. dc-dc load a nd power efficiency the dcdc0 module on sim3l1xx devices is a dc-dc buck co nverter with an input rang e of 1.8 to 3.8 v and an output range of 1.25 to 3.8 v. the efficiency of this regulator changes based on load and the converter configuration, as shown in figure 4. the converter configuration can be changed dynamically or bypassed according to the anticipated demands of the application to maintain the highest power efficiency and reduce power consumption. figure 4. reducing power consumption with the dc-dc buck converter there are three ranges of operation for the dc-dc converter corresponding to three different load sizes: 1. loads less than 5 ma 2. loads between 5 and 15 ma 3. loads greater than 15 ma when operating with loads less than 5 ma, the dc-dc converte r is most efficient when configured for light loads: 1. power switch size set to 0 (psmd = 0) 2. asynchronous mode enabled (asyncen = 1) 3. minimum pulse width set to 40 ns (minpwsel = 3) for loads between 5 and 15 ma, the converter should be set in a middle configuration: 1. power switch size set to 0 (psmd = 0) 2. synchronous mode enabled (asyncen = 0) 3. minimum pulse width disabled (minpwsel = 0) current (ma) power efficiency (%) 50% 55% 60% 65% 70% 75% 85% 80% 0 1020304050 90% 100 90 80 70 60 configured for low loads configured for high loads
AN725 6 rev. 0.1 to configure the converter for loads greater than 15 ma: 1. power switch size set to 3 (psmd = 3) 2. synchronous mode enabled (asyncen = 0) 3. minimum pulse width disabled (minpwsel = 0) table 1 shows a summary of these settings for each load configuration. after configuring the dc-dc converter for the load size, switch the appropriate ldos to the converter output to reduce system power. each of the three ldos (memory, di gital, and analog) can be switched to the battery voltage (vbat) or the dc-dc converter output independently. the firmware can adjust the dc-dc conv erter configuration based on the anticipated load for the active time. for example, if only a few peripherals will be active and the core will halt for a pe riod of time, then the load may be less than 5 ma. firmware can adjust the dc-dc converter appropriately during this period. if the core is fetching instructions from flash at full speed a nd executing a math routine, then switching to the hi gh load configuration will yield lower power consumption. for extremely light loads (less than 2-3 ma), the dc-dc converter will be less efficient than the ldos at ~50% efficiency, depending on the vbat voltage and ldo bias settings. when this occurs, th e dc-dc converter should be bypassed (ben = 1), which connects vbatdc to vdc, or disabled (dcdcen = 0). table 1. dc-dc load configurations load power switch size (psmd) synchronous or asynchronous (asyncen) minimum pulse width (minpwsel) less than 5 ma 0 asynchronous (1) 40 ns (3) 5 ma to 15 ma 0 synchronous (0) disabled (0) greater than 15 ma 3 synchronous (0) disabled (0)
AN725 rev. 0.1 7 5. reducing power consum ption in low power modes in low power mode, the device core halts and the number of active peripherals typica lly reduces to the minimum required by the application (i.e., real time clock). this section discusses techniques to reduce the sim3l1xx device power consumption in low power modes (pm2, pm3, pm6, and pm8). 5.1. sim3l1xx low power mode overview the sim3l1xx devices feature seven low power modes in addition to normal operating mode. several peripherals provide wake up sources for these low power modes, in cluding the low power timer (lptimer0), rt c0 (alarms and oscillator failure noti fication), comparator 0 (cmp0), advanced capture counter (acctr0), lcd vbat monitor (lcd0), uart0, low power mode charge pump failure, and pmu pin wake. in addition, all peripherals can have their clocks disa bled to reduce power consumption with the clock control (clkctrl) registers whenever a peripheral is not being used. the sim3l1xx devices have the power modes defined in table 2. 5.1.1. normal mode (power mode 0) normal mode encompasses the typical fu ll-speed operation. the power consumpt ion of the device in this mode will vary depending on ahb/apb clock speeds, the settings of clkctr l and the perip herals, and the dc-dc converter and ldo settings. 5.1.2. power mode 1 power mode 1 occurs when the core executes code from ram instead of flash. the power consumption of the device is less than normal mode when in pm1. 5.1.3. power mode 2 in power mode 2, the core halts and the peripherals run at full speed. to place the device in this mode, the clock settings in clkctrl should remain the same as normal or power mode 1 and the core should execute a wfi or wfe instruction. if the wfi instruction is called from an interrupt service routine, the interrupt that wakes the device from pm2 must be of a sufficient priority to be recogn ized by the core. it is recommended to perform both a dsb (data synchronization barrier) and an isb (instruction synchronization ba rrier) operation prior to the wfi to ensure all bus a ccess is complete. 5.1.4. power mode 3 fast wake power mode 3 fast wake occurs when all the clocks ar e stopped except for the lfosc0 or rtc0tclk. the core and the peripherals are halted in this mode. the available wake up sources to wake from pm3 are controlled by the power management unit (pmu). the available wake up sources are: low power timer (lptimer0), rtc0 (alarms and oscillator failure notifica tion), comparator 0 (c mp0), advanced ca pture counter (acctr0), lcd vbat monitor (lcd0), uart0, and pmu pin wake. any reset event will also wake the device from pm3. if the wfi instruction that wakes the device from pm3 fast wake is called from an interrupt service routine, the interrupt that wakes the device from pm3fw must be of a sufficient priority to be recognized by the core. by keeping the core clock running at a slow frequency in pm3 and changin g the ahb and apb clocks to the low power oscillator, the de vice can wake up faster than in standard power mode 3 at the expense of higher power consumption. 5.1.5. power mode 3 power mode 3 occurs when all the clocks are stopped, and the core and the peripherals are halted. waking from pm3 requires one of the pmu wake sources described in ?5.1.4. power mode 3 fast wake? to be properly configured. if the wfi instruction is called from an interrupt service routine, the interrupt that wakes the device from pm3 must be of a sufficient priority to be recognized by the core. 5.1.6. power mode 4 power mode 4 is the same as normal operation except the ahb clock operates at a slower speed. the power consumption of the device in this mode will vary depe nding on the ahb/apb clo ck speeds, the settings of clkctrl and the peripherals, and th e dc-dc converter and ldo settings.
AN725 8 rev. 0.1 5.1.7. power mode 5 power mode 5 is the same as pm1 with a slower ahb clo ck source selected. the core executes code from ram instead of flash. the power consumption of t he device in pm5 is slightly less than pm4. 5.1.8. power mode 6 in power mode 6, the core halts and the peripherals run at a slower speed than pm2. to place the device in this mode, the clock settings in clkctrl should remain the same as pm4 or pm5, and th e core should execute a wfi or wfe instruction. if the wf i instruction is called from an interrupt se rvice routine, the inte rrupt that wakes the device from pm6 must be of a sufficient priority to be recognized by the core. 5.1.9. power mode 8 in power mode 8, the core and most peripherals are halted, most clo cks are stopped, and re gisters retain their state. in addition, the ldo regulators are disabled, so all active circuitry operates directly from vbat. alternatively, the pmu has a specialized vbat-divided-by-2 low power mode charge pump that can power some internal modules while in pm8 to save power. the fully operational functions in this mode are: lptimer0, rtc0, uart0 running from rtc0tclk, port match, advanced capture counter, and the lcd controller. this mode provides the lowest power consumption for the device, but requires an appropriate wake up source or reset to exit. the available wake up or reset sources to wake from pm8 are controlled by the power management unit (pmu). the available wake up sources are: low power timer (lpt imer0), rtc0 (alarms and oscillator failure notification), comparator 0 (cmp0), advanc ed capture counter (acctr0), lcd vbat monitor (lcd0), uart0, low power mode charge pump failure, and pmu pin wake. the available reset sources are: reset pin, vbat supply monitor, comparator 0, comparator 1, low power mode charge pump failure, rtc0 oscillator failure, or pmu wake event. to enter this mode, firmware must write the sleepdeep bit in the arm syst em control register. firmware must then execute a wfi or wfe instruction. the core will remain in pm8 until an enabled wake up or reset source occurs.
AN725 rev. 0.1 9 table 2. sim3l1xx power modes mode description mode entrance mode exit normal ? core operating at full speed ? code executing from flash power mode 1 (pm1) ? core operating at full speed ? code executing from ram execute code from ram jump to code in flash power mode 2 (pm2) ? core halted ? ahb and apb operate at full speed for peripherals wfi or wfe instructio n nvic or wic wakeup power mode 3 fast wake (pm3fw) ? all clocks stopped except lfosc0 or rtc0tclk ? ahb and apb set to low power oscillator ? core clock set to lfosc0 or rtc0tclk ? dmactrl0 disabled ? fast wake mode enabled in pm3cn ? ahb switched to low power oscillator ? wfi or wfe instruction requires a wake up source or reset defined by the pmu power mode 3 (pm3) all clocks stopped ? dmactrl0 disabled ? clocks disabled in pm3cn ? wfi or wfe instruction requires a wake up source or reset defined by the pmu power mode 4 (pm4) ? core operating at slower speed ? code executing from flash ? set the ahb clock to a slower source set the ahb clock to a faster source power mode 5 (pm5) ? core operating at slower speed ? code executing from ram ? set the ahb clock to a slower source ? execute code from ram set the ahb clock to a faster source or jump to code in flash power mode 6 (pm6) ? core halted ? ahb and apb operate at a slower speed for peripherals ? set the ahb clock to a slower source ? wfi or wfe instruction nvic or wic wakeup power mode 8 (pm8) ? low power sleep ? the ldo regulators are disabled and all active circuitry operates directly from vbat ? the following functions are available: acctr0, rtc0, uart0 running from rtc0tclk, lptimer0, port match, and the lcd controller ? register state retention ? sleepdeep set in the arm system control register ? wfi or wfe instruction requires a wake up source or reset defined by the pmu
AN725 10 rev. 0.1 5.2. measuring power this section discusses the hardware setup and code requ ired to reproduce the power specifications reported by the sim3l1xx data sheet. 5.2.1. hardware setup to measure the power on the sim3l1xx mcu card with a fixed 3.3 v vbat: 1. connect a usb debug adapter to the 10-pin coresight connector (j14). 2. remove the three sh orting blocks from j7. 3. remove the jp2 imeasure shorting block and put a multimeter acro ss (positive side on the bottom pin). 4. move the vbat sel switch (sw2) to the middle +3.3 v_vreg position. 5. move the vio sel (sw8) and viorf sel (sw9) switches to the bottom vbat position. 6. connect the 9 v powe r adapter to power (j6). 7. download the code to the board. 8. remove the debug adapter connection. 9. measure the power of the device. figure 5. sim3l1xx mcu card power measurement configuration?fixed vbat usb debug adapter 1 2 3 6 9 v power adapter 4 5
AN725 rev. 0.1 11 to measure the power on an sim3l1xx mcu card with a varying vbat: 1. connect a usb debug adapter to the 10-pin coresight connector (j14). 2. remove the three sh orting blocks from j7. 3. remove the jp2 imeasure shorting block. 4. move the vbat sel switch (sw2) to the bottom bat position. 5. move the vio sel (sw8) and viorf sel (sw9) switches to the bottom vbat position. 6. (optional) place a battery in the bt1 holder. 7. (optional) instead of a battery, connect the positi ve terminal of a bench power supply to the positive terminal of the multimeter, the negative terminal of the power supply to the mcu card ground, and the negative terminal of the multimeter to the top pin of the imeasure jumper (jp2). this configuration will prevent any circuitry on the board from interfering with the power measurement. 8. download the code to the board. 9. remove the debug adapter connection. 10. measure the power of the device. figure 6. sim3l1xx mcu card power measurement configuration?varying vbat +000.0075 adc 2.8 v usb debug adapter 1 2 3 6 4 5 9 7
AN725 12 rev. 0.1 5.2.2. configuring a device for normal (pm0) and power mode 4 in normal (pm0) and power mode 4, the device executes code from flash. the only difference between pm0 and pm4 is the core clock speed (fast and slow, respectively). to configure a device to run in pm0 or pm4: 1. enable the clocks to periphera ls that will be configured by firmware. 2. select the desired clock so urce (lposc0, pll0, etc.) and speed for both ahb and apb clocks. 3. select the desired adaptive voltage scaling settings using the ldo module. 4. (optional) disable the retent ion mode of any enabled ram banks. 5. set the pins in the lowest power configuration for this mode. 6. disable all unused peripherals. 7. disable the clocks to all unused peripherals. 8. jump to code in flash. to measure the data sheet numbers using an sim3 l1xx mcu card and the AN725_powermodes_0_and_4 example: 1. configure the sim3l1xx mcu card according to the instructions in ?5 .2.1. hardware setup?. 2. open the AN725_powermodes_0_and_4 example in either keil vision or the precision32 ide. 3. select the desired settings using the #defines at the top of the file. there is a set of defines for each data sheet specification. 4. compile and download the code to the device. 5. disconnect the usb debug adapter. 6. reset the device. 7. measure the power consumption of the device. 5.2.3. configuring a device for power modes 1 and 5 in power modes 1 and 5, the device executes code from ram rather than flash. the only difference between pm1 and pm5 is the core clock speed (fast and slow, respectively). keil vision uses a scatterfile with a re tention ram tag defined as mcu_ram_code: mcu_iram +0 { .any (+rw +zi) .any (mcu_ram_code) } the project source file can then define a tag in code to place functions in this section of memory: #define __si32_rram __attribute__ ((section("mcu_ram_code"))) any functions that use the __si32_rram tag in the definition will be placed in ram star ting at 0x2000_0000: __si32_rram void run_pm1(void) { ... } for precision32 projects, a function can be located in ram by treating it like normal data and applying a data
AN725 rev. 0.1 13 section attribute tag to it. __attribute__ ((__section__(".data. name "))) this tag will result in a warning indica ting that code is being placed in the data section, but this warning can be ignored. as an example, placing the powermod es_2_or_6() function in ram would look like: __attribute__ ((__section__(".data.pm2_or_6"))) void powermodes_2_or_6(void) { ... } there are two ways to access the function in ram: dire ct call or function pointer. direct calls can cause some issues with debugging the code in ram, and the debugger may just step over the function instead of stepping into it. to work around this, single step at the instruction level, set a breakpoi nt in the ram code, or use a function pointer. to configure a device to run in pm1 or pm5: 1. enable the clocks to periphera ls that will be configured by firmware. 2. select the desired clock so urce (lposc0, pll0, etc.) and speed for both ahb and apb clocks. 3. select the desired adaptive voltage scaling settings using the ldo module. 4. (optional) disable the retent ion mode of any enabled ram banks. 5. set the pins in the lowest power configuration for this mode. 6. disable all unused peripherals. 7. disable the clocks to all unused peripherals. 8. jump to code in ram. 9. (optional) disable the ahb clock to the flash controller. to measure the data sheet numbers using an sim3 l1xx mcu card and the AN725_powermodes_1_and_5 example: 1. configure the sim3l1xx mcu card according to the instructions in ?5 .2.1. hardware setup?. 2. open the AN725_powermodes_1_and_5 example in either keil vision or the precision32 ide. 3. select the desired settings using the #defines at the top of the file. there is a set of defines for each data sheet specification. 4. compile and download the code to the device. 5. disconnect the usb debug adapter. 6. reset the device. 7. measure the power consumption of the device. the code executes from ram in this mode, so all functions called should also be in ram.
AN725 14 rev. 0.1 5.2.4. configuring a device for power modes 2 and 6 for power modes 2 and 6, the core halts and no longer exec utes code, but the active peripherals still run from the apb clock. the only differ ence between pm2 an d pm6 is the apb clock speed (f ast and slow, respectively). to configure a device to run in pm2 or pm6: 1. enable the clocks to periphera ls that will be configured by firmware. 2. select the desired clock so urce (lposc0, pll0, etc.) and speed for both ahb and apb clocks. 3. select the desired adaptive voltage scaling settings using the ldo module. 4. disable power mode 8 in the clock control module. 5. (optional) disable the retent ion mode of any enabled ram banks. 6. set the pins in the lowest power configuration for this mode. 7. set up the wakeup interrupt source (including priority). 8. disable the systick timer to preven t these interrupts fr om waking the core. 9. disable all unused peripherals. 10. disable the clocks to all unused peripherals. 11. jump to code in ram. 12. execute the dsb (data synchronization barrier), is b (instruction synchronization barrier), and wfi (wait for interrupt) or wfe (wait for event) instructions. for sim3l1xx devices, wfi and wfe have the same behavior. to measure the data sheet numbers using an sim3 l1xx mcu card and the AN725_powermodes_2_and_6 example: 1. configure the sim3l1xx mcu card according to the instructions in ?5 .2.1. hardware setup?. 2. open the AN725_powermodes_2_and_6 example in either keil vision or the precision32 ide. 3. select the desired ahb clock rate usin g the #defines at the top of the file. 4. compile and download the code to the device. 5. disconnect the usb debug adapter. 6. reset the device. 7. press pb1.7 to place the device in pm2 or pm6. the pb1.5 led will turn off. 8. measure the power consumption of the device. 9. press pb1.5 to wake the device from pm2 or pm6. when this happens, the pb1.7 led will turn on and the core will sit in an infinite while(1) loop. the interrupt that wakes the core from the halted state must have sufficient priority if the wfi or wfe instruction was called from within an isr.
AN725 rev. 0.1 15 5.2.5. configuring a device for power mode 3 fast wake in pm3 fast wake, all clocks are stopped except for a very low frequency clock (rtc0osc or lfosc0) that allows the core to wake up faster than standard pm3. to configure a device to run in pm3 fast wake: 1. enable the clocks to periphera ls that will be configured by firmware. 2. select the desired adaptive voltage scaling settings using the ldo module. 3. disable power mode 8 mode in the clock control module. 4. set the ahb clock to the low power oscillator (lposc0). 5. select the fast wake clock source using the pm3csel field in the clkctrl pm3cn register. 6. enable fast wake mode by setting the pm3cen bit to 1 in the pm3cn register. 7. (optional) disable the retent ion mode of any enabled ram banks. 8. set the pins in the lowest power configuration for this mode. 9. set up the desired pmu wakeup source. 10. put all of the ldos in low bias mode. 11. clear the pmu wakeup flags. 12. disable the systick timer. 13. disable all unused peripherals. 14. disable the clocks to all unused peripherals. 15. execute the dsb, isb, and wfi or wfe instructions. for sim3l1xx devices, wfi and wfe have the same behavior. to measure the data sheet numbers using an sim3l1xx mcu card and the AN725_powermode3_fast_wake example: 1. configure the sim3l1xx mcu card according to the instructions in ?5 .2.1. hardware setup?. 2. open the AN725_powermode3_fast_wake example in either keil vision or the precision32 ide. 3. select the desired ahb clock rate usin g the #defines at the top of the file. 4. compile and download the code to the device. 5. disconnect the usb debug adapter. 6. connect pb0.2 to pb1.5 using a short wire and the j21 and j22 headers. 7. reset the device. 8. press pb1.7 to place the device in pm3fw. the pb1.5 led will turn off. 9. measure the power consumption of the device. 10. press pb1.5 to wake the device from pm3fw. wh en this happens, the pb1.7 led will turn on and the core will sit in an infinite while(1) loop.
AN725 16 rev. 0.1 5.2.6. configuring a device for power mode 8 pm8 is the lowest power mode where all clocks are stopped and only the pm8 peripherals are available. the ram banks do not have retention enabled by default, so firmware must enable each bank to retain data through pm8. for most applications, it is recommended to enable rete ntion for all ram banks, but the specific bank containing the stack pointer must be enabled to ensure proper code op eration on an exit from pm8. see ?5.5. retention ram? for more information on changing the location of the stack pointer. to configure a device to run in pm8: 1. enable the clocks to periphera ls that will be configured by firmware. 2. enable pm8 mode by setting the pmsel bit to 1 in the clkctrl config register. 3. set up the desired pmu wakeup source. 4. switch the ahb clock to the 20 mhz low power oscillator and adjust th e flash read timing as necessary. 5. enable the retention mode of ram banks need ed by the application (all eight banks recommended for most applications). note: to properly execute code after exiting pm8, the stack poin ter must be located in a ram bank with retention enabled. 6. set the pins in the lowest power configuration for this mode. 7. set all ldos to 1.5 v for vbat between 1.8 to 2.9 v and to 1.9 v for vbat between 2.0 to 3.8 v output. 8. (optional) if vbat is between 2.0 to 3.8 v, set the vbat monitor threshold to the high setting. 9. set up the low power peripherals as desired (rtc0, acctr0, lcd0, etc.). 10. (optional) if using the rtc in low-frequency oscillator mode, enable the rtc0 modu le using the steps in the reference manual. if using th e rtc in crystal mode, the recomme nded initialization sequence is: a. disable rtc0 automatic gain control (agc) and enable the bias doubler. b. set up the rtc0 in crystal mode using the list of steps in the reference manual. c. (optional) enable the charge pump (see step 10). d. enable rtc0 automatic gain control and disable the bias doubler. 11. (optional) configure and enable the charge pump: a. enable the low power charge pump monitor in the pmu. b. enable the rtc0 clock to other modules (clkoen = 1 in the rtc0 module). c. enable the low power charge pump monitor as a reset source. d. set the low power charge pump load to the appropriate value for the application. see ?5.3. low power mode charge pump? for more information. e. enable the low power charge pump and enable it as a pmu wake up source. f. enable the low power ch arge pump interrupt. 12. disable all undesired reset sources. note: the watchdog timer (wdtimer0) and pvtosc0 modules will behave as if a power-on reset occurred after exiting pm8, so disabling the watchdog timer as a reset source will prevent unwanted resets. 13. disable the systick timer. 14. disable all unused peripherals. 15. (optional) disable the clocks to all unused peripheral s. entering pm8 stops all cl ocks, so this step is not necessary for this mode. 16. clear the pmu wakeup flags. 17. enable the interrupts for the pmu wakeup source (enabled in step 3). 18. set the sleepdeep bit in the core. 19. execute the dsb, isb, and wfi or wfe instructions. for sim3l1xx devices, wfi and wfe have the same behavior.
AN725 rev. 0.1 17 to measure the data sheet numbers using an sim3 l1xx mcu card and the AN725_powermode_8 example: 1. configure the sim3l1xx mcu card according to th e instructions in section ?5.2.1. hardware setup?. 2. open the AN725_powermode_8 example in either keil vision or the precision32 ide. 3. select the desired ahb clock rate usin g the #defines at the top of the file. 4. compile and download the code to the device. 5. disconnect the usb debug adapter. 6. connect pb0.2 to pb1.5 using a short wire and the j21 and j22 headers. 7. power down the board. 8. power up the board. this will caus e a power-on reset that will clear t he settings of some modules (i.e., pmu). 9. press pb1.7 to place the device in pm8. the pb1.5 led will turn off. 10. measure the power consumption of the device. 11. press pb1.5 to wake the device from pm8. when this happens, the pb1.7 led will turn on and the core will sit in an infinite while(1) loop.
AN725 18 rev. 0.1 5.3. low power mode charge pump the sim3l1xx devices feature a low-power, voltage-halv ing charge pump used to power most of the functions operating in the lowest power mode (pm8). this charge pump always powers the low-frequency and 32 khz crystal oscillators. when in pm8, this char ge pump also powers the following digital comp onents: rtc counters and alarms, lptimer0, uart0, acctr0, retention ram ban ks, lcd0, and the power management unit (pmu) and reset controllers. when not in pm8, these modules are powered by the memory regulator (ldo0). the analog circuitry of the lcd and pulse counter is always powered directly from the vbat pin. the low power mode charge pump is a voltage-halving ci rcuit which reduces the sleep-mode supply current using two methods: 1. it provides approximat ely vbat divided-by-2 to the oscillators a nd digital logic, redu cing their inherent power consumption. 2. it provides a transformer effect which causes the cu rrent pulled from the vbat input to be ideally one-half of the current actually consumed by the circuitry powered by the charge pump. this charge pump can be modeled as a vbat divide d-by-2 supply with a series impedance of r cpload . equation 1 shows the equation for the output voltage of the charge pump. equation 1. charge pump output voltage the value of r cpload depends on the output drive setting field (cpload) in the pmu module and the clock selected by the rtc0 module, as shown in table 3. all circuitry powered by the char ge pump operates correctly at v cp voltages greater than or equal to 0.95 v. thus, for a given charge pump load current, equation 2 must be true. equation 2. charge pump output voltage requirement in all applications with a vba t voltage of 2.4 v or above, the charge pump can operate at its minimum drive impedance (cpload = 3). however, as shown in table 3, the overhead current consumed by the charge pump increases as its drive impedance decrease s. therefore, at lower values of i load , the total pm8 current consumption can be reduced by increasing the charge pu mp?s drive impedance. in addition, since a higher drive impedance corresponds to a lower output voltage for a given load current, increasing the drive impedance also reduces the current consumed by the load circuitry. at higher temperatures, using the low power charge pump and rtc0 can help reduce the leakage current of the device. reducing cpload can further redu ce the leakage at these temperatures. table 3. charge pump output drive settings cpload field r cpload value overhead current lfosc (16.4 khz) rtcosc (32 khz) lfosc (16.4 khz) rtcosc (32 khz) 0 ~600 k ? ~300 k ? ~0 na ~0 na 1 ~200 k ? ~100 k ? ~25 na ~50 na 2~90 k ? ~45 k ? ~50 na ~100 na 3~40 k ? ~20 k ? ~75 na ~150 na v cp vbat 2 ---------------- i load r cpload ? ? = vbat 2 ---------------- i load r cpload ? ? 0.95 v ?
AN725 rev. 0.1 19 5.3.1. monitor the sim3l1xx devices include a low-power voltage monitor that compares the output of the low power mode charge pump against a factory-trimmed 0.95 v reference voltage. this monitor can serve as an interrupt, a pm8 wakeup source, and a reset source. it is highly recommended that this monitor be enabled and used as a wakeup or interrupt sour ce. however, if equation 2 will always be true under all valid operating co nditions, the monitor is not strictly required. leaving the monitor disabled introdu ces the risk that the device could lock-up, requiring an external reset or power cycle to recover. this can occur if the select ed rtc0 oscillator is disturbed and stops oscillating, thereby causing the charge pump output to fail. since the charge pump powers the rtc0 oscillators, the rtc fail notification is not sufficie nt to detect this condit ion, and it will not correct itself without external intervention. the charge pump voltage monito r consumes approximately 15 na, when enabled. when used as a wakeup and interrupt source, the charge pump monitor can alert the firmware that the charge pump output is nearing 0.95 v. this may occur as temper ature rises, for example, causing additional thermal leakage from the pm8 circuitry. the firmware can resp ond by decreasing the charge pump drive impedance by increasing cpload, assuming the drive is not yet at its mi nimum. otherwise, firmware must either reduce the pm8 load (by disabling ram banks or other pm8 active modules) or place the charge pump in bypass mode. when changing the charge pump m ode, it is recomme nded that all digital logic using th e rtc0 oscillators be temporarily disabled. otherwise, a glitch from the oscillators due to the sudd en change in the charge pump output may disturb the logic?s operation. 5.3.2. measuring pm8 charge pump current to measure the charge pump load current, use cmp0 to detect the output voltage of the charge pump during pm8. this output voltage, combined with an adc measurement of the vbat value, can help estimate the present charge pump load in pm8. to do this: 1. enable the charge pump with cpload set to 3. 2. configure the charge pump monitor to wake up and interrupt the device. 3. configure cmp0 to wake and interrupt the device if the charge pump output voltage is equal to 16 x vbat/ 64 (0x10) using the comparator dac feature. 4. schedule an rtc0 alarm to wake and interrupt the device in 1 ms. 5. enter pm8 and wait for a wakeup event. 6. if the wakeup event occurred from the voltage monitor, this indicates the present vbat voltage is too low to operate the charge pump. the charge pump should be configured for bypass mode and this measurement aborted. 7. if the wakeup event was the comparator, change the cmp0 to compare against 8 x vbat/64 (0x08). 8. if the wakeup event was the rtc0 alarm, change the cmp0 to compare against 24 x vbat/64 (0x18). 9. repeat this process starting at step 4, cont inuing to change the cmp0 dac using a successive- approximation method to obtain a 5-bit digital val ue for the charge pump output voltage, where 0x1f corresponds to 31 x vbat/64. 10. use the saradc0 module to measure the voltage on the vbat input. 11. calculate the estimated charge pump load cu rrent using equation 1, the vbat and final cmp0 dac value, and the appropriate value for r cpload . if the resulting load current is small enough that the next lowest setting of cpload results in a charge pump output greater than 0.95 v, this sequence can be repeated with cpload set to 2 to obtain a more accurate measurement of the load current, and so forth.
AN725 20 rev. 0.1 5.3.3. dynamic charge pump drive impedance the low power mode charge pump supports four drive impedance settings. for applications requiring aggressive pm8 current reduction, these settings can be adjusted dynamically to minimize the total low power mode current consumed. this adjustment could be performed by meas uring the charge pump load current as described in section 5.3.2 before each entry into pm8 and setting the appropriate drive impedance. however, a faster and simpler method is available. the charge pump dynamic scaling method consists of two parts: 1. determine when the drive impedance should be decreased by using the charge pump voltage monitor. each time the monitor trips, firmware should reduce the drive impedance setting. if the setting is already at its minimum, firmware can place the charge pump in bypass mode or disable active pm8 circuitry. 2. determine when the drive impedance can be increased. on a regular but relatively infrequent basis, firmware can determine if the cpload setting can be decreased by one without causing the charge pump output to fall below 0.95 v as described in this section. the output state of the charge pump in pm8 is given by equation 1. the required state of the charge pump if cpload is reduced by 1 is given by: equation 3. charge pump output voltage at an increased impedance in equation 3, the r cpload-1 term is the drive impedance for cpload -1. putting these equations together and solving for i load gives: equation 4. minimum charge pump output voltage to increase drive impedance equation 4 provides the minimum v cp value for the present cpload setting that allows cpload to be reduced by 1 without the output dropping below 0.95 v. using this equation, the cmp0 dac setting that corresponds to this equation can be written as: equation 5. cmp0 dac setting for minimum charge pump output voltage to increase drive impedance on a regular basis, firmware can perform the following steps: 1. use the saradc0 module to measure vbat. 2. set the cmp0 dac to the value determined by equation 5. 3. configure cmp0 to wake and interrupt the device if the charge pump output voltage is less than the cmp0 dac. 4. schedule an rtc0 alarm to wake and interrupt the device in 1 ms. 5. enter pm8 and wait for a wakeup event. 6. if the wakeup event was the comparator, cpload should not be reduced by 1. otherwise, cpload can be reduced by 1. equation 4 includes some safety margins that might not be immediately obvious, since it assumes that the charge pump load current is independent of the charge pump output voltage. in fact, the pm8 circuitry requires less current as its supply lowers. sinc e reducing cpload by 1 will decrease the ch arge pump output volt age, the resulting output voltage should always be greater than 0.95 v, assuming equation 4 is satisfied. vbat 2 ---------------- i load r cpload 1 ? ? ? 0.95 v ? ---------------- 1 r cpload r cpload 1 ? -------------------------------- ? ?? ?? 0.95 v r cpload r cpload 1 ? -------------------------------- ?? ?? + ? ? -------------------------------- ? ?? ?? 64 0.95 v ? vbat ----------------------------- - r cpload r cpload 1 ? -------------------------------- ?? ?? + ?? ?? =
AN725 rev. 0.1 21 5.4. lcd for applications that use the lcd0 module, the sim3l1xx devices have several features that help reduce power consumption. 5.4.1. segment resetting each segment of an lcd can be modeled as a capacitor in the order of tens of pf. a typical load current is 1 na per segment per pf, so a 160-segment lcd with 50 pf per segment can draw 8 a of load current. the sim3l1xx devices include a segment resetting fe ature to reduce this load current. fi gure 7 illustrates the basic architecture model of an lcd. figure 7. lcd model lcd segments are energized (i.e., turn opaque) by ac potential waveforms between the segment and the common signal for that segment. these waveforms transition betw een 0 and 3 v, for example, which results in an amplitude of ?3 to 3 v on the segment, depending on the phase of the segment and common waveforms. figure 9 shows an example of the common waveforms for 4-mux mode. to turn on a segment, the controller drives the segment to 3 v or 0 v when the common is driven to 0 v or 3 v, which leads to 3 v on the segment. to turn a segment off, the controller drives the segment to 1 v or 2 v when the common signal is 0 v or 3 v, which leads to 1 v on the segment. most lcd controllers transition direct ly from the most positive amplitude (3 v) to the most negative amplitude (?3 v), as shown in figure 8. this behavior leads to extr a charge being pulled from the battery, since the battery must drive a 6 v transition overall. figure 8. traditional lcd segment transition com0 com1 com2 com3 seg0 seg1 seg7 seg6 seg5 seg4 seg3 seg2 segment +3 v 3 v 3 v +3 v 3 v 3 v -3 v 3 v 3 v segment
AN725 22 rev. 0.1 figure 9. lcd common waveforms for a 4 mux lcd architecture, figure 9 demonstrates that three of the four commons are at the same potential in every phase. this potential is 2 v fo r the even phases and 1 v for the odd phases. instead of the traditional segment switching method, the sim3 l1xx devices reset the segments to 2 v for even phases and 1 v for odd phases before switching to the next segment potenti al to reduce the overall load current of the lcd. the waveforms shown in figure 10 show the sim3l1xx segment resetting behavior in the common and segment waveforms. the areas marked in red are the reset events to the 1 v or 2 v potential, depending on the phase. overall, this reset waveform scheme reduces the current load of an lcd by ~40%, regardless of the number of segments in the display. power-conscious applications using an lcd should enable this feature (rphen = 1) and set the number of rtc0 clocks to reset the segment (rphmd field) using the lcd0 segcontrol register. generally, a rphmd value of 2 provides significant power savings without introducing visual artifacts. however, it is recommended to try a range of values to find the best value for a given lcd. figure 10. sim3l1xx lcd waveforms with segment resetting com0 com1 01 6 5 4 3 27 phase com2 com3 0 v 3 v 2 v 1 v 2 v 1 v 2 v 1 v 0 v 3 v 2 v 1 v 2 v 1 v 2 v 1 v 0 v 3 v 2 v 1 v 2 v 1 v 2 v 1 v 0 v 3 v 2 v 1 v 2 v 1 v 2 v 1 v com0 seg0 01 6 5 4 3 27 phase 0 v 3 v 2 v 1 v 2 v 1 v 2 v 1 v 0 v 3 v 2 v 1 v 2 v 1 v 2 v 1 v
AN725 rev. 0.1 23 5.4.2. contrast modes the lcd0 module features four cont rast modes: bypass, mini mum, constant, and auto-bypass. the selection of the contrast mode is governed by the application requi rements and lcd specificati ons. the power consumption of these modes will vary due to the inte rnal charge pump and resistor stri ng that generates the vlcd voltage. reducing the time this hardware is active will reduce power consumption. in bypass mode shown in figure 11, the vlcd voltage tracks with the vbat input voltage. this mode reduces power consumption by disabling the lcd charge pump and is most appropriate for systems where the vbat voltage is relatively constant. figure 11. lcd0 bypass contrast mode in minimum contrast mode shown in figure 12, the vlcd voltage will track the vbat voltage to a minimum level set by the vbat monitor thresh old (vbmth). when vbat is equal to this voltage, vlcd will switch to the contrast level set by the ctrst field. the threshold and contrast voltages do not have to be set to the same level, as shown in figure 13. if the vbat voltage goes back above the threshold, the lcd contrast charge pump will turn off. this mode is most efficient for systems that can use t he battery voltage most of the time but require a minimum contrast level to see the lcd segments. figure 12. lcd0 minimum contrast mode figure 13. lcd0 minimum contrast mode with different threshold and voltage settings vbat vlcd vbat vlcd minimum level set by ctrst vbat vlcd ctrst vbmth
AN725 24 rev. 0.1 in constant contrast mode, the vlcd voltage is held consta nt at all times, regardless of the voltage on vbat. when vbat is above the threshold set by the vbmth field, the lcd charge pump regulates to the contrast level set by the ctrst field using a variable resistor. when vbat reaches the threshold, the charge pump enables automatically to keep vlcd at the desi red value. this mode results in the highest power consumption, but may be required by some system and lcd architectures. figure 14. lcd0 constant contrast mode in auto-bypass contrast mode shown in figure 15, the vl cd voltage is held constant and tracks the vbat voltage below the threshold. when vbat is above the thre shold voltage set by vbmth, vlcd regulates to the programmed contrast voltage (ctrst) using a variable resistor between vbat and vlcd. when vbat reaches the monitor threshold, the controller automatically enters bypass mode and powers vlcd directly from vbat. the charge pump is always disabled in this mode, and the th reshold and contrast levels do not have to be set to the same value, as shown in figure 16. figure 15. lcd0 auto-bypass contrast mode figure 16. lcd0 auto-bypass contrast mode with different threshold and voltage settings for lowest power consumption, applic ations should use bypass or minimu m contrast modes whenever possible. vbat vlcd vbat vlcd vbat vlcd ctrst vbmth
AN725 rev. 0.1 25 5.4.3. refresh rate the lcd0 module on sim3l1xx devices includes a progra mmable refresh rate by setting the clkdiv bits in the clkcontrol register. the lcd mult iplexor mode must be taken into account when determining the prescaler value. the lcd power consumption will scale proportionally with the refres h rate. for maximum power savings, choose the slowest lcd refresh rate and the minimu m lcd0 clock frequency that provides acceptable performance for the application. for the least flicker, choose a fast lcd refresh rate. 5.5. retention ram the retention ram on sim3l1xx devices is in eight 4 kb b anks. all eight banks are available when not in pm8, but can be individually powered down when in pm8. the current leakage of the ram at higher temperatures may increase, so disabling any unused banks when entering a low power mode may reduce system power consumption. for most applications, it is recommended to enable retent ion for all ram banks. the specific bank containing the stack pointer must be enabled to ensure proper code operation on an exit from pm8. 5.5.1. adjusting the stack pointer with keil vision with keil vision projects, the stack location can be controlled in the scatterfile. the default linker_sim3l1xx_arm.sct scatterfile can be found in the c:\silabs\32bit\si32- x . y . z \si32hal\sim3l1xx directory, where x is the major si32hal version, y is the minor version, and z is the trivial version. inside the scatterfile: arm_lib_stack (si32_mcu_ram_base + si32_mcu_ram_size) the value in the parentheses after the arm_lib_stack l abel is the location of the stack pointer in memory. change this value as needed for the application and ensure this ram bank has retention enabled. 5.5.2. adjusting the stack pointer with the precision32 ide in the precision32 ide, projects can use a custom linker scri pt file edited manually or th e ide dialogs to modify the stack pointer address. to add a custom linker script file manually: right-click on the project name in the project explorer view and select new ? folder . this folder must use the linkscripts name. copy the link_template.ld file from the precision3 2 installation directory ..\ide\precision32\wizards\linker to the project?s linkscripts folder. open the project?s link_template.ld file and ed it the stack line near the bottom of the file: provide(_vstacktop = __top_${data} - ${stack_offset});
AN725 26 rev. 0.1 for example, to locate the stack at address 0x2000_6000: provide(_vstacktop = 0x20006000); instead of editing the link scripts file, the stack offset change can be made inside the ide: 1. right-click on the project_name in the project explorer view. 2. select properties . 3. click on c/c++ build ? settings ? tool settings tab ? mcu linker ? target and input the desired stack offset into the stack offset field. this offset will occur from the t op address of ram, and the value must be a multiple of 4. figure 17 shows this dialog in the precision32 ide. figure 17. using the precision32 ide to select the project library after changing either the custom linker script or ide settings , clean and rebuild the project. view the map file for the project to verify the stack location changed as desired.
AN725 rev. 0.1 27 6. general power-saving tips 6.1. pins placing any unused pins in analog mode using the pbstd module (pbmdsel.x = 0) disables the drivers and weak pull-ups on the pin. the pi n will float and consume little power. for pins that are connected to external hardware, place the pins in analog mode if possible. if this is not possible, place the pins in a natura l state that will consume no power. for exam ple, if a pin has an external pull-down resistor, putting a ?0? in the latch will dr aw no current from the external pull-down. if the system configuration allows it, disabling weak pull-ups on a port-by-port basis may also help reduce unnecessary power consumption in the pins. 6.2. peripherals before entering the low power mode, disable any unwanted peripherals. stopping the clock to the peripheral may disable the peripheral, but if the peri pherals operate on a clock independent from the ahb or apb clocks, only the peripheral registers will be disabled. disabling the module explicitly (d cdcen = 0 for the dcdc0 module, for example) will ensure the module does not dr aw extra power in the low power mode. 6.3. biases in addition to peripherals, disable an y unneeded bias sources in the device before entering the low power mode. these biases draw current to provide voltage references inside the chip. one example of a bias is the 1.2/2.4 v vref0 module or the adc internal 1.65 v voltage reference. 6.4. clocks external oscillators require a bias to start and maintain oscillation. if possible, switching to the internal oscillators and stopping the external oscillato r will reduce the power cons umption. the internal precision oscillator also requires extra current to op erate. in most cases, s witching the ahb and apb clock to the low power oscillator (lposc0) or rtc0 oscillato r before entering the low power mode will result in t he lowest power consumption. the sim3l1xx devices feature programmable clocks for each peripheral. when entering a low power mode, disabling the clocks to any unused peripherals w ill reduce the system power consumption.
AN725 28 rev. 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal solutions . silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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